Low Power, Area Efficient Architecture for Successive Cancellation Decoder

DOI: https://doi.org/10.24003/emitter.v10i1.650
Keywords: Polar Codes, Channel Coding, Successive Cancellation Decoder, FPGA, ASIC

Abstract

Polar codes have recently emerged as an error-correcting code and have become popular owing to their capacity-achieving nature. Polar code based communication system primarily consists of two parts, including Polar Encoder and Decoder. Successive Cancellation Decoder is one of the methods used in the decoding process. The Successive Cancellation Decoder is a recursive structure built with the building block called Processing Element. This article proposes a low power, area-efficient architecture for the Successive Cancellation Decoder for polar codes. Successive Cancellation Decoder with code length 1024 and code rate 0.5 was designed in Verilog HDL and implemented using 45-nm CMOS technology. The proposed work focuses on developing an area-efficient Successive Cancellation Decoder architecture by presenting a new Processing Element architecture. The proposed architecture has produced about 35% lesser area with a 12% reduced gate count. Moreover, power is also reduced by 50%. A substantial reduction in the latency and improvement in the Technology Scaled Normalized Throughput value was observed.

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Published
2022-06-20
How to Cite
Sujanth Roy J, & G Lakshminarayanan. (2022). Low Power, Area Efficient Architecture for Successive Cancellation Decoder. EMITTER International Journal of Engineering Technology, 10(1), 170-182. https://doi.org/10.24003/emitter.v10i1.650
Issue
Vol 10 No 1 (2022)
Section
Articles

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